This latest generation processor family features devices with 16 to 100 identical processor cores (tiles) interconnected with Tilera’s iMesh™ on-chip network. Each tile consists of a complete, full-featured processor as well as L1 and L2 cache and a non-blocking switch that connects the tiles into the mesh. As with all Tilera® processors, each tile can independently run a full operating system, or multiple tiles taken together can run a multiprocessing OS like SMP Linux.
The TILE-Gx family processor slashes board real estate requirements and system costs by integrating a complete set of memory and I/O controllers, eliminating the need for an external north bridge or south bridge. TileDirect™ technology provides coherent I/O directly into the tile caches to deliver ultimate low-latency packet processing performance. Tilera’s DDC™ (Dynamic Distributed Cache) system for fully coherent cache across the tile array enables scalable performance for threaded and shared memory applications.
This is something I will need to read up about, the 100 core processor possibility sounds outstanding, what I need to further understand is the processor compatibility with existing platforms and therefore the ability to run it in parallel environments, a mixed current and legacy operating environment. For cloud and new build outs, with the application code ported and optimized, systems based on these processors (like those of the Power and Cell/B.E) could be a compelling offering.